View ATA5279N_4757589.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Features
* Six Connections for Series-resonant LF Coil Antennas * Drives up to 1A Peak Current on the First Three Channels and up to 700 mA Peak on * * * * * * * *
the Second Three, Largely Independent of the Battery Voltage On-off-keyed Data Modulation with up to 6 kbit/s Sinusoidal-like Output Signal for Superior EMC Behavior 20 Selectable Steps for Current Regulation for Field Strength Measurement (RSSI) Output Driver Stages are Protected Against Electrical and Thermal Overload Very Low Power-down Current Consumption SPI Interface for Easy Microcontroller Bus Connection LF Data Buffer to Minimize Microcontroller's CPU Load During a Data Transmission Small Outline Package: QFN48, 7 mm x 7 mm
1. Description
The ATA5279N is an LF coil driver IC intended for passive entry/-go (PEG) systems. It can drive up to six low-frequency-antennas (i.e., coils) to provide a wake-up and initialization channel to the key fob. Figure 1-1. Block Diagram
VS VCC VL PGND VDS
Antenna Driver for Multiple Antennas ATA5279N Preliminary
OSCI
Oscillator Internal Supply POR, BG, UV/OV
Boost Controller
DC DC
HP 1-3
A1P A2P A3P
OSCO
S_CS S_CLK MOSI MISO
SPI LF Data Buffer
Sine Wave Generator
LP 1-3
A4P A5P A6P
VIF NRES IRQ BCNT MACT
Control Logic Communication Protocol Handling
Driver Stage Control
Return Line Driver Integrator
A1N A2N A3N A4N A5N A6N VSHF
Sample and Hold Reference
Zero Cross Detector
GND
RGND
CINT
VSHS
9125F-RKE-09/09
2. Pin Configuration
Figure 2-1. Pinning QFN48
VL3 PGND3 VL2 PGND2 VL1 PGND1 VDS3 IRQ NRES S_CLK S_CS MOSI VS RGND CINT VCC VSHS VIF OSCI OSCO MACT BCNT VSHF1 A6N1 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 33 4 32 5 6 31 7 30 8 29 9 28 27 10 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24
ATA5279N
MISO AGND3 A6P A3P A5P AGND2 A2P A4P AGND1 VDS2 A1P A1N2
Table 2-1.
Pin Heat Slug 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Pin Description
Symbol PGND VS RGND CINT VCC VSHS VIF OSCI OSCO MACT BCNT VSHF1 A6N1 A6N2 A3N1 A3N2 A5N1 A5N2 VSHF2 A2N1 A2N2 Function Backside ground connection Battery supply pin Reference ground Integration capacitor connection Analog 5V stabilization capacitor connection Shunt resistor voltage sense input Digital supply voltage input Oscillator input pin Oscillator output pin Modulator active indicator output pin LF-bit counter output pin Shunt resistor driving pin 1 Coil 6 negative connection line pin 1 Coil 6 negative connection line pin 2 Coil 3 negative connection line pin 1 Coil 3 negative connection line pin 2 Coil 5 negative connection line pin 1 Coil 5 negative connection line pin 2 Shunt resistor driving pin 2 Coil 2 negative connection line pin 1 Coil 2 negative connection line pin 2 Pin Group CSP CSP DO DO RLO LRL LRL HRL HRL LRL LRL RLO HRL HRL
2
ATA5279N [Preliminary]
9125F-RKE-09/09
A6N2 A3N1 A3N2 A5N1 A5N2 VSHF2 A2N1 A2N2 VDS1 A4N1 A4N2 A1N1
ATA5279N [Preliminary]
Table 2-1.
Pin 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Pin Description (Continued)
Symbol VDS1 A4N1 A4N2 A1N1 A1N2 A1P VDS2 AGND1 A4P A2P AGND2 A5P A3P A6P AGND3 MISO MOSI S_CS S_CLK NRES IRQ VDS3 PGND1 VL1 PGND2 VL2 PGND3 VL3 Function Driver supply pin 1 Coil 4 negative connection line pin 1 Coil 4 negative connection line pin 2 Coil 1 negative connection line pin 1 Coil 1 negative connection line pin 2 Coil 1 positive connection line pin Driver supply pin 2 Driver ground pin 1 Coil 4 positive connection line pin Coil 2 positive connection line pin Driver ground pin 2 Coil 5 positive connection line pin Coil 3 positive connection line pin Coil 6 positive connection line pin Driver ground pin 3 Master-In-Slave-Out SPI output pin Master-Out-Slave-In SPI input pin SPI chip select pin SPI clock input pin Chip reset input pin Interrupt request output pin Driver supply pin 3 Boost converter low-side switch output 1 Boost converter low-side switch input 1 Boost converter low-side switch output 2 Boost converter low-side switch input 2 Boost converter low-side switch output 3 Boost converter low-side switch input 3 Pin Group DS LRL LRL HRL HRL HDL DS LDL HDL LDL HDL LDL DO DI DI DI DI DI DS BLS BLS BLS
3
9125F-RKE-09/09
3. Functional Description
3.1 Operation Modes
ATA5279N features five operation modes. They are: * Power-down mode (reset state) * Idle mode * Operating mode * Shutdown mode * Diagnosis mode Power-down mode is active after supply voltages have been applied to the chip. No internal circuitry is active in this mode and as such power consumption is minimal. If no operation of the chip is demanded, it should be kept in this state. To enter power-down mode, a negative pulse on the NRES pin for at least tNRES,min is required. After wake-up from power-down mode by a logic high signal at the S_CS pin, the chip is in idle mode. That is, the oscillator is running and the control logic waits for commands coming from the serial interface. Furthermore, the selected output driver stage is ready for operation (the voltage on the corresponding output pin AxP is approximately half the battery supply voltage). The current consumption of the chip is now mainly defined by the cross current through the active driver stage (please refer also to Section 3.2 "Coil Driver Stage" on page 5). When processing coil driving commands, the chip is in operation mode. From the interface point of view, there is no difference from the idle mode; however, current consumption is now higher as the output driver stages are operating and, depending on the selected output current, the DC-DC converter is also operating. If a connection failure (short circuit on any of the coil connection lines) is detected, the ATA5279N enters the shutdown mode to protect itself from damage. In this mode, the interface operates in idle mode but with all power stages shutdown and no LF transmission command processing. This mode should be exited using the Reset Fault Status command (see below), however, it can also be exited by resetting the chip. In diagnosis mode, the output driver stages are also disabled. In their place, high-ohmic current sources are activated that can be programmed via the serial interface in order to check the coil connection lines for failures. This mode can be exited by an appropriate SPI command or by resetting the chip.
4
ATA5279N [Preliminary]
9125F-RKE-09/09
ATA5279N [Preliminary]
3.2 Coil Driver Stage
The driver stage for each coil consists of two N-channel DMOS transistors. The low-side transistor is in Darlington configuration to maintain a source-follower characteristic. Figure 3-1. Principle Driver Stage Setup
VDS
IHS
IHSDiag
Diag Enable Nmirr VSin_pre AxP
Pmirr1 Pmirr2 Npwr Internal nodes
Ax_State
Diag Enable
ILS GND
ILS
ILSDiag
In the graphic above, the names of internal pins have a grey shaded background, and the hatched area is not part of the driver stage itself but only used in diagnostic mode (please refer to the Diagnosis Block description for further information on this topic). The driver stages are supplied by the three VDS pins, which are tied together inside the chip. A quiescence current regulation ensures low cross current while in idle state. The output transistors are monitored for current and temperature to protect them from damage caused by irregular load conditions or too high ambient temperatures. The driving stage is optimized for signal quality to ensure low harmonic distortions. Two groups of driver stages are integrated: the first group is intended for high-current coils, whereas the second group drives low-current coils. Note that there are certain coil impedance ranges for each driver group. If the connected load exceeds this range, proper current regulation and/or data modulation is not guaranteed. While in idle mode and especially during a transmission, the driver stages of the five inactive (i.e., not selected) coils are switched to high-side outputs, i.e., the positive coil connection lines are tied to the VDS potential. The same applies to the return line inputs AxN. These measures ensure minimum parasitic currents in the disabled coils while the selected coil is operating.
5
9125F-RKE-09/09
3.3
Sine Wave Generator
The sinusoidal coil-driving signal is internally generated. Its amplitude is dependant on the measured coil current, and the frequency is derived from the oscillator stage. In conjunction with the output driver stages, the generated signal is optimized for low harmonic distortions. The peak-to-peak amplitude of the sinusoidal signal is directly defined by the voltage on the external integration capacitor connected to the CINT pin. This voltage, with an offset subtracted, is internally used to generate a low-voltage sine wave signal, which is in turn amplified and level-shifted up to the desired output level. The output signal itself has a DC offset close to the half of the supply voltage, and the maximum possible amplitude has about 3V distance to each of the supplies. Figure 3-2 illustrates this. Figure 3-2. Maximum Possible Coil Driving Signal for a Given Supply Voltage VDS
VDS VOUT,max
0.5 x VDS
VOUT,min GND
In application, the output coil current is the fixed valued (selectable via SPI). Hence, the required output voltage is calculated as follows:
V Out,p = I Coil,p x ( Z Coil + R DSon,HRS/LRS + R Shunt )
Here, ZCoil is the complex impedance of the coil, RDSon,HRS/LRS is the on-resistance of the appropriate return line current selector (see also Section 7. "Functional Parameters" on page 31) and RShunt is the resistance of the externally applied current sense shunt resistor (typ. 1, see also Section 4. "Application" on page 26).
6
ATA5279N [Preliminary]
9125F-RKE-09/09
ATA5279N [Preliminary]
3.4 Boost Converter
The coil driver stage can be supplied by a DC-DC converter in boost configuration. Together with an externally applied choke, freewheeling diode and capacitor, the battery voltage can be brought up to the required value, which is dependant on the coil's impedance and the selected current. The converter is only enabled during an active transmission. The peak current through the low-side switch IVL and the output voltage VVDS are measured to shut down the converter operation in case one of the values exceeds its upper limit.
Note: There is no dedicated temperature monitoring for the boost converter low-side switch. For further details, please refer to the section "Application Hints" on page 27.
The switching frequency is, like the coil driving signal, derived from the oscillator stage and 125 kHz in value when using an 8 MHz input clock. The least possible time the boost converter takes to generate the maximum possible output voltage from the minimum possible input voltage is dependant on several parameters. The values of the external components (choke inductance, charge capacitance and CINT integration capacitance) greatly effects this time.
3.5
Coil Current Sensing (Zero Cross, Sample and Hold, Integrator)
The coil current flows through an external shunt resistor, causing a current-dependant voltage, which is fed into the IC via the VSHS pin. By monitoring the zero crossing events of this signal, the phase of the coil current is known and hence the positive peak value can be sampled. The peak coil current is then subtracted from an internal reference voltage that is dependant on the selected coil current, which results in the regulation difference. An amplifier stage converts this difference into a current, which is then fed into an externally applied integration capacitor connected to the CINT pin. The resulting voltage on this capacitor directly influences the amplitude of the sine wave signal. It also determines the supply voltage generated by the boost converter, if the necessary coil supply voltage exceeds the actual supply voltage level. Note that during an active transmission, this voltage is internally limited to VCINT,max. Note that in idle mode, the voltage on the integration capacitor is kept at a value that corresponds to the battery supply voltage. This ensures that the boost converter, if needed, always performs a soft start from the battery voltage level on. The desired current can be selected via the SPI. A total of 20 predefined steps are available, divided into the following sections: * The lower four steps (50 mA to 200 mA) are intended for the low-current coils only * The next ten steps (250 mA to 700 mA) are intended for both types of coils * The upper six steps (750 mA to 1A) are intended only for the high-current coils The IC allows the use of a current step not intended for a particular driver group; however, in this case, full functionality, especially a stabilized coil current, cannot be guaranteed. See also the Control Logic block description for an overview over the commands.
7
9125F-RKE-09/09
3.6
Diagnosis
The diagnosis stage monitors both the positive (AxP) and negative (AxN) connection lines of the six coils. If one of these lines is shorted to battery supply or to ground, the following measures are taken for protection and diagnostic reasons: * All coil driver stages are shut down, i.e., put into high impedance state * The shunt resistor is disconnected from the coil return lines * The reason for the fault shutdown is stored in the fault register * An interrupt request is triggered (see also control logic block) In addition to short circuits, a disconnected coil (i.e., open load) or an excessive junction temperature can also lead to such a fault shutdown. Note that this type of diagnosis is carried out continuously during normal operation of the IC to protect both the IC and the peripherals from damage. It must be avoided to design the system's load profile in such a way that the protection features of the chip are triggered under normal operating conditions. Consecutive triggering of the overtemperature shutdown may lead to a reduced lifetime. In the event of such a fault shutdown, the IC can be brought back to operation by resetting its fault register with the appropriate SPI command (please refer also to the Section 3.9.2 "General Command Description" on page 20 later in this document). As a result, transmission on nonfaulty coils is still possible even if there is a failure of one coil. Beyond this, the diagnosis of all connected coil lines is a very useful tool for maintenance reasons. The ATA5279N has implemented test structures that can be activated and read out via SPI commands, so that the microcontroller can be programmed to detect most of the possible faults, for example, shorts between different coil connection lines and multiple shorts in one pair of lines.
3.6.1
Functional Description of Diagnosis Mode In this diagnosis mode, the coil-line drivers themselves are switched to high impedance. Hence, only the test structure at every coil connection (both at the positive outputs AxP of the drivers and at the negative outputs AxN) is present and can directly test the status of the line. Figure 3-3 illustrates this:
8
ATA5279N [Preliminary]
9125F-RKE-09/09
ATA5279N [Preliminary]
Figure 3-3. Base Structure of the Diagnosis Module of One Output Channel
VDS VDS
S_HxP c0 = '1' AxP AxN
S_HxN c1 = '1'
c0 bit
S_LxP c0 = '0'
S_LxN c1 = '0'
c1 bit
AGND
AGND
Latch
Driver x select c0, 1 bits
The structure above can be found in each of the six channels of ATA5279N. As soon as the diagnosis mode is engaged, all channels are operated in this way. On the channel that is actually selected, the setting of the switches can be changed with the Set Coil Current command and the status of the two connection lines can be checked with the Get Driver Setup command. The two switches in the P line driver are controlled with one bit. That means, either the high-side (S_HxP) or the low-side (S_LxP) switch is closed. The same is true for the N line driver (S_HxN, S_LxN). The controlling bits c0 and c1 are taken from the coil current selection register (see Section 3.9.2 "General Command Description" on page 20 in this document). Note that the setting of the switches is latched. That means, if the setting on the switches of the selected driver is changed, the setting on the five other channels remains unchanged. By a combination of test structures, many different faults, even between the coils, can be detected. As described in the principle schematic of a driver stage above, a test structure consists of two switchable current sources (one to VDS and one to GND) and a comparator that converts the voltage level on the line into a digital signal. The switches for the current sources can only be controlled in diagnosis mode, with the corresponding coil being selected (see also Driver Command description). Note that one switch is always closed, either the high-side or the low-side switch of one test structure. These structures are independent, i.e., they can be set up for each line individually and at the same time. The status of the connection lines of the selected coil can be read out with a SPI command. In the following example, there is a short circuit between the positive coil connections of coil 1 and 2.
9
9125F-RKE-09/09
Figure 3-4.
Example 1, Using the Diagnosis Mode
VDS
S_H1P A1P
S_H2P
RShort
A2P
S_L1P
S_L2P
Status_1
Status_2
GND
Taking the circuit situation shown above, the test run starts with both S_L1P and S_L2P switches closed (default state when entering the diagnosis mode for the first time). The read-back of the line state result in both times 0, which is not unexpected. However, the result does not change when either altering the channel 1 or the channel 2 switch setting. That can be caused both by the failure shown above and by short-circuits of both lines to ground. The final diagnosis can be identified by changing both channels to the high-side switches (S_H1P and S_H2P). In this case, the two status lines both return 1s - which eliminates the possibility of two short-circuits to ground. Table 3-1 summarizes this test sequence.
10
ATA5279N [Preliminary]
9125F-RKE-09/09
ATA5279N [Preliminary]
Table 3-1.
Step 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Note:
Sequence for Example 1, Using the Diagnosis Mode
Command Select Driver Get Driver Setup Select Driver Get Driver Setup Set Coil Current - no command Get Driver Setup Select Driver Set Coil Current - no command Get Driver Setup Select Driver Set Coil Current - no command Get Driver Setup I O 01101000 - 68h 00000010 - 02h I O I I 01101000 - 68h 00001001 - 09h 00101010 - 2Ah 10100000 - A0h I O I I 01101000 - 68h 00000010 - 02h 00101001 - 29h 10100001 - A1h I/O I I O I I O I Coding 00101001 - 29h 01101000 - 68h 00000001 - 01h 00101010 - 2Ah 01101000 - 68h 00000010 - 02h 10100001 - A1h Actions/Remarks Selects driver 1 with Diagnosis Mode enabled Reads back active driver info: Channel 1 active, both lines return a 0 Selects driver 2 with Diagnosis Mode enabled Reads back active driver info: Channel 2 active, both lines return a 0 Closes test switches S_H2P and S_L2N Note: S_L2P and S_H2N are then open Wait for the test structures to stabilize in the new setting, see below Reads back active driver info: Channel 2 active, but both lines return a 0 Selects driver 1 with Diagnosis Mode enabled Closes test switches S_H1P and S_L1N (Note: S_L1P and S_H1N are then open) Wait for the test structures to stabilize in the new setting, see below Reads back active driver info: Channel 1 active and A1P returns a 1 Selects driver 2 with Diagnosis Mode enabled Closes test switches S_L2P and S_L2N Note: S_H2P and S_H2N are then open Wait for the test structures to stabilize in the new setting, see below Reads back active driver info: Channel 2 active and A2P returns a 1
Steps 6, 10 and 14 are wait states, as the test structures need some time to stabilize in their new setting. This depends mainly on the externally applied capacitors on the AxP and the AxN pins.
The suggested waiting time is calculated as follows:
2 x V S x ( C e + C ant ) t diag,wait = ----------------------------------------------------300 A
The sequence above is an example of how the failure illustrated in Figure 3-4 on page 10 could be detected. Depending on the grade of detection detail that is required, a matrix for the test sequence should be set up to find the most effective way of programming and testing. For more details on the commands, please refer also to Section 3.9.2 "General Command Description" on page 20.
11
9125F-RKE-09/09
The second example circuit has two faults in the circuitry. Figure 3-5. Example 2, Using the Diagnosis Mode
VDS
RShort1
S_H4P A4P A4N S_H4N
S_L4P
S_L4N
RShort2
Status_4
Status_4N
GND
If channel four is activated in normal operation, a fault shutdown will occur. The reason for this shutdown (i.e., the entry in the fault register) could either be an overload on the A4P line (here a short circuit to VS) or a short-circuit on the A4N line to VS. In any case, the IC protects itself and the external components from damage; however, the fact that there is more than one failure in the wiring cannot be discovered. In diagnosis mode, by testing the A4P line with S_H4P and S_L4P, the short circuit to VS could be found first. The same result would be found when testing the return line switch 4 accordingly, so the presence of more than one fault on coil 4 is determined. The precise fault cannot be found though. The diagnosis result would be the same both for the above shown circuit and for the A4N line being directly shorted to VS (without the failure in the coil module, here RShunt2) and for the combination of the two.
12
ATA5279N [Preliminary]
9125F-RKE-09/09
ATA5279N [Preliminary]
Table 3-2.
Step 1 2 3 4 5 6 7 8
Sequence for Example 2, Using the Diagnosis Mode
Command Select Driver Get Driver Setup Set Coil Current - no command Get Driver Setup Set Coil Current - no command Get Driver Setup I O 01101000 - 68h 00010101 - 15h I O I 01101000 - 68h 00011101 - 1Dh 10100000 - A0h I/O I I O I Coding 00101101 - 2Dh 01101000 - 68h 00011101 - 15h 10100010 - A2h Actions / Remarks Selects driver 4 with Diagnosis Mode enabled Reads back active driver info: Channel 4 active, A4N returns a 1 Closes test switches S_L4P and S_H4N Note: S_H4P and S_L4N are open then Wait for the test structures to stabilize in the new setting, see first example Reads back active driver info: Channel 4 active, both lines return a 1 Closes test switches S_L4P and S_L4N Note: S_H4P and S_H4N are open then Wait for the test structures to stabilize in the new setting, see first example Reads back active driver info: Channel 4 active and A4N returns a 1
Again, this is only an example of how the diagnosis system can be used. Generally, a more systematic approach is suggested in order to efficiently test all connection lines used.
Note: To exit the diagnosis mode correctly, two SPI commands have to be sent: the first is the Select Driver command with the DM bit set to 0 and the second is a Reset Fault Status command. See also SPI Command Description.
3.7
SPI
The SPI is used to select the required coil and its current, to provide LF data to the IC, to select and start an LF transmission, and to read out status information. It is equipped with a chip select input to enable or disable communication. When disabled, the data output of the IC is in high impedance mode, so other devices may communicate on the same bus. The interface is configured as a slave device, always requiring a master (e.g., a microcontroller) for operation. The maximum input clock frequency is 1/4 of the system clock present at the OSCI pin, resulting, for example, in a maximum signal speed of 2 Mbit/s when using a typical 8 MHz input clock. The SPI features four different operation modes, which only differ in the relationship between the clock signal (S_CLK) and the data I/Os. Both the SPI itself and the corresponding I/O lines are supplied by the application-provided logic supply voltage connected to the VIF pin. This ensures that the controller (master) and the IC (slave) operate with the same voltage levels. In total, four modes of operations are possible, each differing in clock polarity and phase. Figure 3-6 and Figure 3-7 illustrate this.
13
9125F-RKE-09/09
Figure 3-6.
SPI Operation in POL = 0 and PHA = 0 Mode
Sample
S_CS
Setup
S_CLK
MISO
Z
X
Z
MOSI
X
LSB
1
2
3
4
5
6
MSB
X
X
Figure 3-7.
SPI Operation in POL = 1 and PHA = 0 Mode
Sample
S_CS
Setup
S_CLK
MISO
Z
X
Z
MOSI
X
LSB
1
2
3
4
5
6
MSB
X
X
Figure 3-8.
SPI Operation in POL = 0 and PHA = 1 Mode
Sample
S_CS
Setup
S_CLK
MISO
Z
X
Z
MOSI
X
X
LSB
1
2
3
4
5
6
MSB
X
14
ATA5279N [Preliminary]
9125F-RKE-09/09
ATA5279N [Preliminary]
Figure 3-9. SPI Operation in POL = 1 and PHA = 1 Mode
Sample S_CS
Setup
S_CLK
MISO
Z
X
Z
MOSI
X
X
LSB
1
2
3
4
5
6
MSB
X
The configuration mode can be selected with the appropriate SPI command (see Section 3.9.2 "General Command Description" on page 20). Note that after power-up or a reset, the IC is always in its default configuration (POL = 1, PHA = 1), which must be used to alter the configuration. At the end of the SPI configuration-changing command, the new configuration is activated with the falling edge of the S_CS signal. 3.7.1 Timing Figure 3-10 illustrates the timing parameters of the SPI communication. Figure 3-10. Timing Parameters of the SPI Communication
tCS,set tIo tCShold tSPIoff
S_CS
thi
S_CLK
MISO
Z
X
X
MOSI
X
LSB tSPI tsetup thold
1
6 tout,valid
MSB
X tMISOoff
X tMISOon
Note:
The diagram above is using POL = 0 and PHA = 0 as a setup for the SPI. The values are also valid for the other three configurations. The limits for the timing values shown above can be found in Section 7. "Functional Parameters" on page 31.
15
9125F-RKE-09/09
3.8
Command Buffer
This buffer is a First-In-First-Out (FIFO)-type buffer, located between the SPI and the modulator stage. The microcontroller can write coil-driving related commands and data with full SPI speed to keep the CPU and bus load low.
3.8.1
Structure The buffer can store up to 128 bits, organized in 16 words, each eight bit in size. Hence, each data word from the SPI that contains a control command for the driver stages (i.e., select a certain driver, select a certain current, transmit LF-data bits and transmit a constant wave) is stored in a buffer word. Figure 3-11 outlines this. Figure 3-11. Structure of 128 bit FIFO Command Buffer
8 From SPI 8 Write Pointer 0 1 8 General Command Processing 2 3 4 5 6 7 8 9 10 11 12 13 14 15
7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 0
Data Selector
128 bit FIFO buffer
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Read Pointer Modulator Stage 8
The read pointer indicates the next word to be processed by the Modulator Stage, whereas the write pointer indicates the next free location for data from the SPI. These pointers are controlled by the internal logic to enable the first-in-first-out functionality. 3.8.2 Usage After wake-up from power-down, the buffer is empty and ready to receive commands and LF data. Any LF command and data is fed into the buffer via the SPI. The buffer can be filled even during an active data modulation, i.e., when some LF data and/or commands remain in the buffer while waiting to be processed. This increases the independency of the coil driver from the microcontroller. An interrupt request (IRQ) is triggered when the fill state of the buffer drops below 25% or if too many words are sent and a FIFO overflow occurs.
16
ATA5279N [Preliminary]
9125F-RKE-09/09
ATA5279N [Preliminary]
Seamless data processing is an important feature of the command buffer. LF data intended for the same coil and the same current step can be distributed to several commands without the risk of having unwanted gaps in the LF telegram. This allows protocols to have any length and is usable both with the Send LF-data and the Send Carrier command. Refer also to the Section 3.9.1 "Modulator Stage" on page 17 for further details.
3.9
Control Logic
The internal control logic handles all information coming from the SPI and controls the power stages. Diagnostic information is also collected and evaluated here.
3.9.1
Modulator Stage The modulator stage controls the coil drivers. It gets all necessary information from the command buffer. That is: * Which coil to drive * Which current to maintain in this coil/which diagnosis switch to close (in diagnosis mode) * Which baud rate to use for LF data transmission * What kind of transmission (i.e., data or carrier) * LF data itself (respectively the on-time when a carrier is to be transmitted) When a modulator operation is started by an SPI command, the data in the buffer is processed in the order it arrives via SPI, command by command. The time for this data processing depends on the command itself and, if LF transmissions are involved, the amount and length of the data bits. Table 3-3 lists the timings for the driver-related commands.
Table 3-3.
Execution Durations of Driver-related Commands
Dur. [LF per.] Comment During the first 32 periods, the actual driver is stopped in order to decay any oscillation in the coil. Then the switching itself is performed and another 32 periods waiting time is started in order to wait for the new driver to reach its operation point The switching time of internal references takes less than 1 LF period. Note that there will always be an interruption in a telegram if the coil current is changed between two transmission commands
Command
Select Driver
64
Select Coil Curr.
<1
Send LF Data
The duration of this command depends on the selected data rate (4 kbit/s, i.e. 32 periods/LF bit, or 5.7 kbit/s, i.e., N x 2 x {32 / 22} 22 periods/LF bit) and the amount of nibbles N (2 LF data bits) to be transmitted T x (32 / 22) The duration of this command depends on the selected data rate (see also above) and the carrier duration T
Send LF Carrier
Note:
Table 3-3 lists the duration of command execution for the different commands and not the decoding or processing time. This is done simultaneous, so that two commands can be executed seamlessly.
17
9125F-RKE-09/09
LF data is transmitted on-off-keyed (OOK). "1" enables the field, whereas "0" disables it. Note that the field generation strongly depends on the bandwidth (the Q factor) of the coil. If it is too narrow, the receiver might not be able to decode the data correctly. Figure 3-12 shows the signal path from the modulator stage to the receiver. Figure 3-12. Example for OOK-data Modulation with ATA5279N
Modulator Data
off 1 0 1 1 1
Transmitter Coil Current
Current Envelope Receiver Detection Thresholds
Receiver Data
off
1
0
1
1
0
1
Coils with high Q values need more periods to reach the desired field strength and hence appropriate detection level thresholds in the receiver. So the Q factor must be adapted in order to ensure proper data communication. For example, the thresholds here are chosen at 70% of the required output current for a 0 to 1 and at 30% for a 1 to 0 detection. The IC supports two data rates: standard, which is 4 kbit/s (or 32 LF periods), and high speed, rated with 5.7 kbit/s (or 22 LF periods). Note that this refers to the encoded (net) data rate. The minimum length of an active field (e.g., the time for the first 1 in Figure 3-12), is 16 LF periods in standard and 11 LF periods in high speed mode (i.e., gross data rate). Another aspect of the LF data transmission is that current regulation can only be done roughly, as the measurement must be interrupted over and over again. At a 0 to 1 transition, the current measurement will not start until the 5th period, and there will not be any measurement during a 0-transmission. The regulation precision that is achieved during carrier transmission is not valid here. As described in Section 3.8 "Command Buffer" on page 16, data is processed seamlessly to avoid gaps in longer LF telegrams. The following example illustrates this feature. Assume that following data words have been written into the command buffer via the SPI: 1. Send 2 LF bits (SPI data 00h 05h) 2. Send carrier with a length of 24 data bits (SPI data 98h)
18
ATA5279N [Preliminary]
9125F-RKE-09/09
ATA5279N [Preliminary]
In this example, the output signal of the modulator resembles the illustration below. Figure 3-13. Example of Data Transmission of Two Consecutive Commands
First Command Second Command
Modulator Data
BCNT Signal 2 x tdata 26 x tdata 24 x tdata
The value for tdata depends on the speed setting of the modulator (32 LF-periods in standard and 22 periods in high speed mode, with one period being 8 s when operating with 125 kHz output frequency and therefore 8 MHz system clock). The least amount of data that can be processed by the modulator stage is four LF bits or two (e.g. Manchester-encoded) data bits. The first command in the upper example is a minimum-length LF data command. To ensure the traceability of the LF protocol, two pins are provided, which indicate an active data transmission (MACT) and the change of an LF bit (BCNT). Figure 3-12 illustrates the function of these two signals: Figure 3-14. LF Transmission Tracing Signals
Modulator Data
off 1 0 1 1 0 1 1 off
Transmitter Coil Current
Current Envelope
MACT Signal
BCNT Signal
The MACT signal can be used to start a timer whereas BCNT can be used as input signal to a counter. Note that for carrier transmissions, only the MACT signal is active. There are not any pulses on the BCNT line.
19
9125F-RKE-09/09
3.9.2
General Command Description The following commands are directly processed by the control logic, i.e., they are not fed into the data buffer:
Table 3-4.
Bit Definitions of the General SPI Commands
Input Word (MOSI Data) MSB MSB LSB Output Word (MISO Data) 6 X F X C3 X D1 X X X 5 4 3 X T X C0 2 X S X DG 1 X Op X D1 LSB X X X D0 X X X
Command Get status info Get driver setup Get fault info Reset fault status Set SPI config Halt operation
6 1 X 1 X 1 X 1 1 1
5 1 X 1 X 1 X 0 0 0
4 0 X 0 X 1 X 0 0 1
3 0 X 1 X 0 X 0 1 0
2 0 X 0 X 0 X 0 0 0
1 0 X 0 X 0 X 0 0
0 X 0 X 0 X 0 0 0
0 X 0 X 0 X 0 0
X R X C4 X DG X X X
X X BO BU X C2 X D0 X X X X C1 X T X X X
X X X X F03 F02 F01 F00 X X X X X X X X X
PO PH
Refer to Section 3.7 "SPI" on page 13 for bit direction definitions. * Get Status Info: This command delivers the general IC status information back to the microcontroller (via the SPI bus). One part of the return word is the interrupt request source. If such a request is active (i.e., the IRQ line is high), the source for it is coded here. * Possible sources include the diagnosis block to indicate a driver stage fault (bit F), a general reset (either triggered externally by the NRES pin or internally by the power-on reset structure, bit R), an overtemperature of the chip (bit T), or the FIFO buffer indicating that the fill state has dropped to 25% or below (i.e., only 4 words are left, bit BU), or the fill state exceeds the upper limit of 16 bytes (bit BO). The IRQ signal is reset with this command. Additionally, the operability flag of the IC (bit Op) is returned in the word. Note that only if no fault is stored in the fault register and all operation voltages are present and valid, the operability is given (indicated by a 1 in the Op bit). Otherwise, ATA5279N will not process any driver-related command. Finally, the LF speed mode bit returned here indicates the current speed state of the modulator stage (bit S, 0 for normal speed, 1 for high speed). bit R: bit F: bit BO: bit BU: bit T: bit S: bit Op Chip reset - either triggered externally by the NRES pin or internally by the power on reset structure Indicator for a driver stage fault The FIFO buffer fill state exceeds the upper limit of 16 bytes The FIFO buffer fill state drops to 25% or below, i.e., only 4 words are left Chip overtemperature indicator LF modulator speed mode indicator LF driver stage operability indicator
20
ATA5279N [Preliminary]
9125F-RKE-09/09
ATA5279N [Preliminary]
* Get Driver Setup: This command returns the actual setup of the driver stage, i.e., the selected coil, encoded in the bits DG,D1..0, and the selected current, which can be found in the bits C4..0 (see also "Select Driver" and "Set Coil Current" command description below for details on bit coding). This command is also used in diagnosis mode to fetch the state of the coil connection lines. * Get Fault Info: This command returns the content of the driver stage fault register back to the microcontroller via the SPI bus. The register contains both the code for the detected fault and the number of the driver stage that was active when the fault occurred. Refer also to the Section 3.9.4 "Status Monitor" on page 24 for further details. * Reset Fault Status: This command clears the content of the driver stage fault register and sets the operability bit in the general state register if all supply voltages are present and valid. This command is necessary to resume normal operation following the occurrence and subsequent removal of a fault. Please note that prior to this command, the active channel should be switched to a line that is not faulty. Otherwise, the internal logic might get corrupted and must then be reset with a negative pulse on the NRES line. Note that this command is also required to bring ATA5279N back into operation mode once the diagnosis mode was active and was then cleared by a Select Driver command. * Set SPI Config: This command changes the two configuration bits PO(L) and PH(A). These bits are responsible for the serial data processing of the SPI. Default: PO = 1, PH = 1 * Halt Operation: As this command is processed immediately, it is not written to the FIFO buffer even if it is a driver-related command. The effect of this command is that the content of the FIFO buffer is cleared, hence no new LF data is available, and if any driver is active it will be stopped. Note that such stops are only carried out at the end of an LF period (i.e., when the sinusoidal output signal reaches half of the supply voltage). 3.9.3 Driver-related Command Description Following commands are processed via the LF data buffer:
Table 3-5.
Bit Definitions of the Driver-Related SPI Commands
Input Word MSB MSB LSB Output Word 2 C2 N2 L2 .. T2 1 D1 C1 N1 L1 .. T1 6 X X X 0 L6 X 5 X X X 0 L5 X 4 X X 3 X X 2 X X 1 X X LSB X X X
Command Select driver Select coil current Send LF data Send LF carrier
6 0 0 0 L6 .. 0
5 1 1 0 L5 .. 0
4 C4 0 L4 .. T4
3 C3 N3 L3 .. T3
0 1 0 L7 .. 1
BR DM DG
D0 C0 N0 L0 .. T0
X X X 0 L7 X
X X X X X 0 N3 N2 N1 N0 L 4 L3 L2 L1 L0 X X X X
21
9125F-RKE-09/09
* Select Driver: This command selects the coil that is to be driven or tested next. The BR-bit indicates the modulation speed (0 for 4 kbit/s, i.e., 32 LF periods and 1 for 5.7 kbit/s, i.e., 22 LF periods). * The DG,1..0 bits indicate the channel number to be activated. DG selects the driver group (0 for high-current driver 1..3, 1 for low-current driver 4..6) and D1..0 the required driver in the group (01 for driver 1 / 4, 11 for driver 3 / 6). For connection line diagnosis, the diagnosis mode can be enabled by setting the DM-bit to 1. bit BR: bit DM:
Notes:
LF modulator speed (0 for 4 kbit/s, i.e., 32 LF periods and 1 for 5.7 kbit/s, i.e., 22 LF periods Diagnosis mode selector (0: Normal LF operation mode, 1: Coil connection diagnosis mode)
1. If set, all coil connections are switched to this mode. Normal operation is not possible. (i.e., LF transmission). The same works for the opposite way: once a Select Driver command is received with the DM-bit at 0, all connection lines are switched back to normal operation mode. 2. For a proper operation after a diagnosis run, a Reset Fault Status command also needs to be sent.
bits DG,1..0: bit DG:
Active channel indicator Driver group selector (0 for high-current driver 1..3, 1 for low-current driver 4..6) bits D1..0: Driver selector , i.e. 01 is driver 1 (DG = 0) / 4 (DG = 1), 11 is driver 3 (DG = 0) / 6 (DG = 1). Default: DG,1..0 = [001], DM = 0, BR = 0 --> Channel 1, diagnosis mode off and normal LF speed selected. * Select Coil Current This command defines the current to be established for the next LF transmissions. bits C4..0: bits C1..C0: Contain the step number in the range of 0 to 19 (00hex to 13hex) Are used in diagnosis mode, to control the test switches of the activated connection line
whereas ... bit C0: The low/high-side switch of the AxP line bit C1: The low/high-side switch of the AxN line) Default: C4..0 = [00000] --> 50 mA coil current selected. * Send LF Data: This command must be used to start an LF data telegram on the selected coil. The bits N3..0 contain the amount of nibbles to be transferred into the LF data buffer of ATA5279N. This amount has to be coded as follows: N3..0 = (nNibbles - 1) Hence, a maximum of 16 nibbles or 8 words and a minimum of 1 nibble can be written into the buffer using one command. Note also that this command uses one more word of space in the buffer, as the header word is also stored. So for example, if the LF telegram consists of four words, the required space in the LF data buffer is five words (four words of pure data and one word for the command header). It is important that the amount of nibbles passed in the header word matches the number of words transferred afterwards to the IC, as no data consistency checking can be carried out here. If an odd number of nibbles is to be transferred, the data word on the SPI has to be completed with dummy data in the upper nibble, as the SPI always requires complete data
22
ATA5279N [Preliminary]
9125F-RKE-09/09
ATA5279N [Preliminary]
words on the bus. The FIFO buffer is also only filled with complete words. For an example, if 7 nibbles of LF data (i.e., 14 LF data bits) are to be sent by ATA5279N via the LF channel, the Send LF Data command consists of five words, the header word (here 06h) and four LF data words, whereas the last word contains only four bits (the four least significant) of the LF data. For an additional example, see Figure 3-15, which illustrates how LF transmission data is processed in ATA5279N. Figure 3-15. LF Data Processing
SPi Data String (hex) SPi Data String (bin)
02h 0000 0010
35h 0 0 1 1 0 1 01
04h 0 1 00
LF Telegram
MACT Signal
BCNT Signal
* Send LF Carrier: This command should be used when a carrier shall be transmitted on the LF channel via the selected coil. The current will be regulated by ATA5279N to the value selected with the last Select Coil Current command (resp. the default value of 50 mA). See also Section 3.5 "Coil Current Sensing (Zero Cross, Sample and Hold, Integrator)" on page 7 for further details. The duration of this carrier can be defined by the T4..0 bits. Note that the time unit here is one LF data bit, i.e., 32 LF periods in normal- and 22 LF periods in high-speed mode. That leads to a maximum definable carrier time per command of 31 x 0.256 ms = 7.936 ms when using an 8 MHz system clock. However, when the T4..0-value is set to 0, an endless carrier transmission with the actually selected current on the actually active coil is started. This can be used for long-term measurements or for energy-coupling purposes. Be aware that long-term transmissions can produce a huge amount of heat in the driver, dependant on the selected coil current and the properties of the coil itself. It is therefore strongly recommended to use this feature only with a maximum current settings of 100 mA; otherwise, the chip temperature might reach excessive values.
23
9125F-RKE-09/09
3.9.4
Status Monitor The status monitor holds all information from the diagnosis stage. In case of an existing fault, all power stages are disabled. As soon as a fault is stored, an interrupt request (IRQ) to the microcontroller is generated. This signal is persistent until the status info is polled by the microcontroller. The entry in the fault register can only be cleared by the Reset Fault command or a global reset. There are two different status registers: * A general IC status register (requestable by the Get Status Info command) * A coil-driver related fault register (requestable by the Get Fault Info command) The fault register is encoded as follows:
Table 3-6.
Fault Register
Fault Assignment between Driver Stages and the Fault Registers
MSB DG D1 D0 T F03 F02 F01 LSB F00
The meaning of the bits is described below: * DG, D1..0: The driver group and number that was active when the fault occurred. Only a selected driver can be affected by external faults. Therefore, it is sufficient to store the type of failure and the corresponding driver number. Refer to Section 3.9.3 "Driver-related Command Description" on page 21 for further details on the coding of these bits. * T: A temperature shutdown has occurred. Note that there is not necessarily a link between the driver number and this fault, as all sensor signals of the chip are OR'ed together. However, in general, it can be assumed that the last active driver also caused the overtemperature condition. * F03: This bit indicates a missing return line signal during modulation. That means that the current detection unit was not able to find a sinusoidal signal on the VSHS pin although the LF coil was driven. The reason for this can either be an open load condition or a short-circuit on the AxN pin towards ground. * F02: This bit indicates an excessive positive voltage on the VSHS pin. In normal applications, this is only the case if there is a high current flowing through the shunt resistor. The typical reason for this is a short-circuit on the AxN line towards battery. Another possible reason could be a shorted LF coil. * F01: This bit indicates an excessive current through the high-side transistor that drives the AxP line. The most typical reason for this is a short-circuit towards ground. * F00: This bit indicates an excessive current through the low-side transistor that drives the AxP line. The most typical reason for this is a short-circuit towards battery.
24
ATA5279N [Preliminary]
9125F-RKE-09/09
ATA5279N [Preliminary]
3.10 Oscillator
This block provides the clock signals internally needed for control logic, the LF driver stage, and the boost converter. The oscillator requires an external clock source, which can either be an active signal from a microcontroller for example, or a passive oscillation device like a crystal or a ceramic resonator. As the LF carrier frequency is directly derived from this clock, the (resonance) frequency of the clock source must be chosen to match the desired LF frequency. Possible values range from 6.4 MHz to 9.6 MHz, where 8 MHz is the typical value resulting in an LF frequency of 125 kHz. Note that during start-up (i.e., as long as no stable oscillation can be detected), the driving current for the crystal is increased to shorten the start-up delay. Furthermore, the IC is only functional if the oscillator is working properly. That means, during start-up after a power-down phase, no communication and no operation of the IC is possible until the oscillator reaches its operation point. If an external clock source such as a microcontroller is to be used, the logic-level clock signal must be applied at the OSCI pin, and the OSCO pin must be left open. Note that the chip protection features, need a clock signal present at the OSCI pin; without this, the chip is not fully protected. Therefore, if the chip is in any mode but in power-down (reset), a clock signal is needed. The oscillator block is, like the control logic and the SPI, supplied by the application-provided logic supply voltage connected to the pin VIF.
3.11
Internal Supply
The internal power supply stage provides all internally needed BIAS currents and reference voltages. An integrated one-time-programming (OTP) structure is used to adjust internal settings. This ensures parameter stability over the production process. The internal supply block performs monitoring functions to reset or shut down the IC in case of supply shortages or during power-up. A power-management minimizes current consumption during power-down mode of the IC. Another part of this block is the internal 5V voltage regulator. It is supplied by the VS pin, i.e., the battery supply connection. This voltage is used for all internal analog functions and driving processes. It is active as long as the IC is not in power-down mode. To increase stability and quality of this supply line, it is externally available (pin VCC) for connection to a ceramic capacitor for filtering and buffering. Note that no loads must be connected to this pin. As with the oscillator, this supply voltage must settle in its operation point prior to any operation. The control logic checks the status of this voltage and inhibits operation until it reaches the required level. Furthermore, the driver supply voltage present on the VDSx pins is also monitored. If the level falls below VVDS,min, the operability flag of the chip is cleared (bit Op in the Status Register) and driver-related commands cannot be processed. Once the voltage level is valid again, the Op bit is set again, and operability is restored.
25
9125F-RKE-09/09
4. Application
Find below a typical application schematic for ATA5279N. Figure 4-1. Application Schematic for ATA5279N
VBATT D1 L1 L2 D2
+
C1 C5 C2 VS VCC VL PGND C4 C3
+
VDS
PCB
OSCI X1 Oscillator OSCO Internal Supply POR, BG, UV/OV Boost Controller
DC DC
car
Ant1 Ant2 Ant3
A1P
HP 1-3
A2P A3P
Ce1 Ce2 Ce3 C voltage supply line (VDD) S_CS S_CLK MOSI MISO SPI LF Data Buffer Sine Wave Generator A4P
LP 1-3
A5P A6P
Ant4 Ant5 Ant6 Ce4 Ce5 Ce6
C connection
C7 VIF NRES IRQ BCNT MACT Control Logic Communication Protocol Handling
Driver Stage Control
A1N Return Line Driver A2N A3N Integrator A4N A5N A6N VSHF Ce7 Ce8 Ce9 Ce10 Ce11 Ce12
Sample and Hold Reference
Zero Cross Detector
GND
RGND
CINT
VSHS
C6
R1
Note:
A negative current on pin MISO that causes the voltage to drop below -0.6V with respect to ground might lead to a chip reset, comparable to a logic low on the NRES pin.
26
ATA5279N [Preliminary]
9125F-RKE-09/09
ATA5279N [Preliminary]
Table 4-1.
Part R1 C1 C2 C3 C4 C5 C6 C7 Ce1..12 D1 D2 L1 L2 X1
Bill of Materials (BOM) for Typical Application Circuit
Value 1 220 F/50V 100 nF cer. 4.7 F/50V tant. 100 nF cer. 100 nF cer. 33 nF cer. 100 nF cer. 1 nF cer. 50V/3A 50V/3A/50 ns 150 H 82 H 8 MHz Description Shunt resistor, 1% tol. Supply line input filter and stabilizing cap Supply line input filter cap Boost converter storage cap, low ESR Boost converter filter cap (+ESD clamp) Internal 5V supply line stabilizing cap Integration cap for current regulation loop Filter cap for C supply line Add. ESD buffer, necessity tbc Rectifying diode High-speed freewheeling diode Supply line input filter choke, Isat > 3A Boost converter charging choke, Isat > 3A Crystal or resonator
4.1
Application Hints
An important application aspect is the thermal budget. Under certain conditions, high power dissipations can occur during operation of the chip. The ATA5279N's power dissipation mainly depends on the supply voltage and the selected antenna output current. Under worst case conditions (e.g., low supply voltage and maximum antenna power) the power dissipation increases exponentially and may rise to values exceeding 10W. It must be avoided under all circumstances to exceed the specified maximum average junction temperature. Therefore, the thermal aspects of the entire application, along with the electrical design, are essential. The thermal resistance between the IC and the ambient has to be designed according to the specific application requirements. It is mandatory to solder the exposed die pad to the PCB. As many vias as possible must be provided between the top and the bottom layer (soldering side to the PCB's backside). This copper plane is able to store and dissipate the heat. It must be electrically connected to ground, and an appropriate heat transfer away from the chip must be ensured. In addition, multi-layer-PCBs (more than two layers) are recommended. The ATA5279N's power dissipation depends on the supply voltage, the selected antenna current, the antenna's impedance and further parameters such as the external components used for the DC-DC converter. Background information, design hints and an example are given in the application note "Thermal Considerations for ATA5279". It is strongly recommended to measure the power dissipation in the target application during the design phase to verify the system's thermal budget. One option is to calculate the difference between input and output power.
27
9125F-RKE-09/09
See the following description for details: P diss,tot = P in - P out P in = U VS x I VBATT Mean value measured during an LF carrier transmission with the desired output current. I Ant,p 2 P out = ------------ x Z Ant + P diss,ext 2 Pdiss,ext is the sum of power dissipated by the external components. I Ant,p U Ant,pp P out = ------------ x ----------------- + P diss,ext 2 2x 2 Alternative formula for calculating the output power.
Note: The output power can either be calculated by using the impedance of the antenna or by measuring the peak-to-peak amplitude of the sinusoidal voltage applied to the antenna. As the impedance may change under load conditions, it is recommended to use the formula with the peak-to-peak antenna voltage.
The input power determination should be done by transmitting a single LF carrier burst with a length of for example 8 ms. The required electrical data needs to be recorded with a digital sampling oscilloscope (DSO) and a current probe. Note that the start-up phase of the LF field must not be used for reading out the data. Figure 4-2. Power Dissipation on Chip Measured at Application Board ATAB5279
14.00
IC Power Dissipation (W)
12.00
10.00
Z(Ant) = 12.5 I(Ant) = 1000 mAp
8.00
6.00 Z(Ant) = 12.5 I(Ant) = 700 mAp
4.00
2.00 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 16.0
Supply Voltage VS (V)
Note:
If the VDS output voltage regulation fails due to too high input currents or too high output voltage, the power dissipation increases up to 40%
The power dissipation of the external components depends on their parameters and the supply current. Regarding choke L2, it is the DC resistance, regarding the freewheeling diode D2, it is the forward biasing voltage. In addition, the equivalent series resistance (ESR) of the charging capacitor C3 is important. The devices' names refer to the application schematic (see Figure 4-1 on page 26).
28
ATA5279N [Preliminary]
9125F-RKE-09/09
ATA5279N [Preliminary]
Note: To define the operation limits, the static thermal resistance of the PCB must be known (see the measurement hints in the application note). The ATAB5279 application board features a total thermal resistance of 42 K/W.
Under worst case conditions, e.g., low supply voltage and high antenna impedance, the maximum antenna current might not be reached. A "static" operation of ATA5279N is not allowed for typical transmit currents of several hundreds of mAs. Typical applications are operated with a temporary LF field, resulting in an on/off operation mode of the chip. A suitable on/off duty cycle nduty reduces the average power dissipation and keeps the thermal budget of the system. Therefore, following equation needs to be fulfilled: T amb + R thJA x P diss,tot x n duty < T j,max with Tamb Pdiss,tot nduty
Note:
the application's maximum ambient temperature the total power dissipation of the chip Operation duty cycle On-time during period, t1/tper
It must be avoided to design the system's load profile in such a way that the protection features of the chip are triggered under normal operating conditions. If the output voltage reaches the upper shutdown limit, the power dissipation of the DC-DC converter increases significantly. Consecutive triggering of the overtemperature shutdown may lead to a reduced lifetime.
In addition to the average junction temperature Tj,max, the maximum peak temperature during a transmission must not be exceeded. The equation to be met is as follows:
1 ------------- PCB 1 - e +n T peak P diss x R thjc + R thca x duty x P diss x ( R thjc + R thca ) + T amb
t
with: Tpeak Rthca t1 tauPCB nduty maximum peak temperature = 200C Thermal resistance case-to-ambient (PCB) Transmission on-time, 10 ms t1 1 sec Thermal time constant of PCB (Rthca x Cthca) Operation duty cycle
29
9125F-RKE-09/09
5. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Voltage range on pin VS Voltage range on pins VDSx, VLx Voltage range on pins AxP Voltage range on pins VSHFx, VSHS Voltage range on pins AxNx Voltage range on pins VCC, VIF Voltage on pins RGND, PGNDx Voltage range on pins NRES, S_CS, S_CLK, MOSI, OSCI, MACT, BCNT, IRQ, MISO, OSCO Voltage range on pin CINT ESD Voltage Ratings - HBM (MIL-STD-883F, M. 3015.7) Maximum average junction temperature Note: All voltages refer to the AGND pins. Symbol VVS VVDS,max VAxP,max VVSHF,max VAxNx,max VDIGSUP,max VGND,max VIO,max VCINT,max VESD Tj.max Min. -0.3 -0.3 -0.3 -3 VVSHF - 0.3 -0.3 -0.3 -0.3 -0.3 2 150 Max. 40 46 VVDS + 0.3 VVCC + 0.3 46 +5.5 +0.3 VVIF + 0.3 VVCC + 0.3 Unit V V V V V V V V V kV C
6. Thermal Resistance
Parameters Thermal resistance junction to case Thermal resistance junction to ambient Note:
(1)
Symbol RthJC RthJA
Value 10 35
Unit K/W K/W
1. Value that can be achieved when providing sufficient thermal vias and heat dissipation area
30
ATA5279N [Preliminary]
9125F-RKE-09/09
ATA5279N [Preliminary]
7. Functional Parameters
All parameters valid for 7.0V VS 16.5V and -40C Ta 105C unless otherwise noted. No. 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 3 3.1 3.2 Parameters Power Supply VS-pin power-down mode supply current VS-pin idle mode supply current Internal VCC voltage - idle - load VS voltage clamp VCC power-on reset threshold VDS operation threshold VS = 16.5V VVS 14V VVS = 16.5V 7V VS 28V IVCC = 0 IVCC = 5 mA VS = 28V VS = 40V 1 1 4 1 4 DS 1 DS DS 1 IVSpd IVS,idle VVCC,0 VVCC,1 IVS,C28 IVS,C40 VPORVCC VVDS,min VVS IVDS,0 IVDS,FS VVS 4.8 50 1.5 4.1 5.1 7 0 0.85 7 0.12 5.15 5.5 3.5 5.05 180 3 10 5 5.3 400 4.5 4.8 6 16.5 1.4 2.45 26.5 A mA V A mA V V V A mA V A A A A A A D A A D Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
Battery supply range for Idle mode normal operation VDS power-down mode VVDS = 28V supply current VDS fault-shutdown mode supply current VVDS = 16.5V
Battery supply range for Idle mode Jump start operation Boost Converter Overvoltage shut-down level Switch overcurrent shutdown level Switch on-state resistance Max duty cycle (ton / T) Switch leakage current VVL = 38V Switch fall time Switch rise time Oscillator External clock source frequency range Driver output sink resistance during startup Driver output sink resistance during operation IOSCO = 100 A IVL = 200 mA IVL = 200 mA IVL = 500 mA
DS BLS BLS BLS BLS BLS BLS
VVDSmax IVLmax RDSon,VL DBoost IVL,leak tVL,f tVL,r
40 2.9
42 3.2
44 4 0.5 0.875 500
V A nA ns ns
A A A A A A A
50 50
200 200
CSP CSP
fOSC ROSC,L1
6.4 0.9
8
9.6 2.2
MHz k
D A
3.3
IOSCO = 100 A
CSP
ROSC,L1
1.8
4.4
k
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. In this column, pin group names are given. Please refer to Section 2. "Pin Configuration" on page 2 in this document for more details. 2. Operation of coils with higher impedance than the given value is possible but functional limitations might occur (inability to reach to configured coil current). Coils with lower impedance should not be used as they might be detected as faulty.
31
9125F-RKE-09/09
7. Functional Parameters (Continued)
All parameters valid for 7.0V VS 16.5V and -40C Ta 105C unless otherwise noted. No. 3.4 Parameters Driver output source resistance during startup Driver output source resistance during operation Feedback resistance Clock input low-to-high detection threshold Power-down input pull-down resistance Sourcing current limit (RMS) Sinking current limit (RMS) VOSCI = 5V VVIF = 5V Test Conditions IOSCO = -100 A Pin CSP Symbol ROSC,L1 Min. 0.9 Typ. Max. 2.2 Unit k Type* A
3.5 3.6 3.7 3.8 4 4.1 4.2 4.3
IOSCO = -100 A VOSCI, OSCO = 5V
CSP CSP CSP 7
ROSC,L1 RFB,OSC VLH,OSC ROSCI,0
1.8 220 0.45 x VIF 3
4.4 360 0.55 x VIF 6
k k
A A A
k
A
High-current Driver Stage (A1P, A2P, A3P) Idle mode, DC ramping Idle mode, DC ramping HDL HDL HDL HDL HRL HDL HDL DS HDL IHP,HSCL IHP,LSCL DSig -1.7 1.1 -0.88 2 -34 A A dB B B A
= 30V V Signal difference carrier AxP,pp Icoil,p = 200 mA to harmonics 2, 3, 4, 5 fOSCI = 8 MHZ Load imped. range (amount of complex impedance)(2) Min. output voltage Max. output voltage Icoil,pp = 2 App IAxP = 200 mA Tj 30C IAxP = -200 mA Tj 30C VVDS = 20V IAxP = 0 IAxP = 200 mA Tj 30C VVDS = 20V IAxP = -100 A
4.4 4.5 4.6 4.7 4.8
ZCoil,HP VOHP,min VOHP,max IAxPH,CC VAxPH,dile
2 2.5 VDS - 4.5 35 9 50
12 4.3 VDS - 2.5 68 11
V V mA V
D A A A A
Idle mode cross current VVDS = 16.5V Idle mode output voltage Inactive pull-up current
4.9 4.10 4.11 5 5.1 5.2
HDL
RAxPH,PU IPU,Diag IPD,Diag
11.5 -150 170
27 -100 260
k A A
B A A
Diagnosis mode pull-up VVDS = 16.5V current VAxP = 0V Diagnosis mode pull-down current Sourcing current limit (RMS) Sinking current limit (RMS) VVDS = 16.5V VAxP = 16.5V
Low Current Driver Stage (A4P, A5P, A6P) Idle mode, DC ramping Idle mode, DC ramping LDL LDL ILP,HSCL ILP,LSCL -1.2 0.9 -0.55 1.7 A A B B
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. In this column, pin group names are given. Please refer to Section 2. "Pin Configuration" on page 2 in this document for more details. 2. Operation of coils with higher impedance than the given value is possible but functional limitations might occur (inability to reach to configured coil current). Coils with lower impedance should not be used as they might be detected as faulty.
32
ATA5279N [Preliminary]
9125F-RKE-09/09
ATA5279N [Preliminary]
7. Functional Parameters (Continued)
All parameters valid for 7.0V VS 16.5V and -40C Ta 105C unless otherwise noted. No. 5.3 Parameters Test Conditions Pin LDL LDL LRL IAxP = 200 mA Tj 30C IAxP = -200 mA Tj 30C VVDS = 20V IAxP = 0 IAxP = 200 mA Tj 30C VVDS = 20 V IAxP = -100 A LDL LDL DS HDL Symbol DSig Min. Typ. Max. -34 Unit dB Type* A = 30V V Signal difference carrier AxP,pp Icoil,p = 200 mA to harmonics 2, 3, 4, 5 fOSCI = 8 MHZ Load imped. range (amount of complex impedance)(2) Min. output voltage Max. output voltage
5.4 5.5 5.6 5.7 5.8
ZCoil,LP VOLP,min VOLP,max IAxPL,CC VAxPL,dile
10 2.5 VDS - 4.5 28 9 40
25 4.3 VDS - 2.5 53 11
V V mA V
D A A A A
Idle mode cross current VVDS = 16.5V Idle mode output voltage Inactive pull-up current
5.9 5.10 5.11 6 6.1 6.2 6.3 6.4 6.5 6.6 7 7.1 7.2
HDL HDL LDL HDL LDL HRL LRL RLO HRL LRL HRL LRL
RAxPL,PU IPU,Diag IPD,Diag
11.5 -150 170
27 -100 260
k A A
B A A
Diagnosis mode pull-up VVDS = 16.5V VAxP = 0V current Diagnosis mode pull-down current Return line switch on-state resistance Return line switch overcurrent shutdown threshold VVDS = 16.5V VAxP = 16.5V IHPS = 0.3A ILPS = 0.22A RShunt = 1 Ch. 1-3 selected Ch. 4-6 selected
Coil Return Line and Diagnosis Stage (A1N ... A6N) RDS,onHPS RDS,onLPS IShunt,max IPU,Diag IPD,Diag TOTsdwn HRL LRL tOLdet 1.25 0.875 -150 170 145 115 1.05 1.2 1.75 1.225 -100 260 170 215 A A A A C s A A A A B A
Diagnosis mode pull-up VVDS = 16.5V current VAxP/N = 0V Diagnosis mode pull-down current Overtemperature shutdown threshold Open load detection delay Zero Crossing Detector Pos. slope detection threshold Switching propagation delay Voltage jump from VVSHS - 20 mV to VVSHS + 20 mV VVDS = 16.5V VAxP/N = 16.5V
5 5
VZC tZCdel
-10 150
+10 290
mV ns
A A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. In this column, pin group names are given. Please refer to Section 2. "Pin Configuration" on page 2 in this document for more details. 2. Operation of coils with higher impedance than the given value is possible but functional limitations might occur (inability to reach to configured coil current). Coils with lower impedance should not be used as they might be detected as faulty.
33
9125F-RKE-09/09
7. Functional Parameters (Continued)
All parameters valid for 7.0V VS 16.5V and -40C Ta 105C unless otherwise noted. No. 8 Parameters Test Conditions Sampling state Current step 20 selected VVSHS = 200 mVpp VVSHS = 1 Vpp Pin Symbol Min. Typ. Max. Unit Type* Sample and Hold Stage
8.1
Sampled differential voltage
5 Vsmpl,1 Vsmpl,2 5 3 Vofs,Integ IINT,POS 830 440 -2.5 -20 970 560 +2.5 -8 mV mV mV A
A
9 9.1 9.2
Integrator Stage Input offset voltage VVSHS = 1.1 Vpp Positive output linearity Current step 20 selected Negative output linearity VVSHS = 0.9 Vpp Current step 20 selected ICINT = 30 A VSHS = 100 mVp Current step 20 selected B A
9.3
3
IINT,NEG
8
20
A
A
9.6
Upper output voltage limit References Current step 1 level Current step 2 level Current step 3 level Current step 4 level Current step 5 level Current step 6 level Current step 7 level Current step 8 level Current step 9 level Current step 10 level Current step 11 level Current step 12 level Current step 13 level Current step 14 level Current step 15 level Current step 16 level Current step 17 level Current step 18 level Current step 19 level Current step 20 level
3
VCINT,max
3.15
3.45
V
A
10 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.11 10.12 10.13 10.14 10.15 10.16 10.17 10.18 10.19 10.20 Notes:
-
VREF,S1 VREF,S2 VREF,S3 VREF,S4 VREF,S5 VREF,S6 VREF,S7 VREF,S8 VREF,S9 VREF,S10 VREF,S11 VREF,S12 VREF,S13 VREF,S14 VREF,S15 VREF,S16 VREF,S17 VREF,S18 VREF,S19 VREF,S20
49.5 97 145 192 245 294 343 392 441 490 539 588 637 686 735 784 833 882 931 980
54.5 105 157 208 255 306 357 408 459 510 561 612 663 714 765 816 867 918 969 1020
mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV
A A A A A A A A A A A A A A A A A A A A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 1. In this column, pin group names are given. Please refer to Section 2. "Pin Configuration" on page 2 in this document for more details. 2. Operation of coils with higher impedance than the given value is possible but functional limitations might occur (inability to reach to configured coil current). Coils with lower impedance should not be used as they might be detected as faulty.
34
ATA5279N [Preliminary]
9125F-RKE-09/09
ATA5279N [Preliminary]
7. Functional Parameters (Continued)
All parameters valid for 7.0V VS 16.5V and -40C Ta 105C unless otherwise noted. No. 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 11.13 11.14 Parameters Supply current in operation mode Supply current in power-down mode SPI clock period SPI clock low-phase timing SPI clock high-phase timing SPI output enabling time SPI output disabling time Minimum SPI disable time Minimum chip select setup time Minimum chip select hold time Minimum data input setup time Minimum data input hold time Output source capability Output sink capability VVIF = 5V ISource = -1 mA VVIF = 5 V Isink = 1 mA Vin = 0 V VVIF = 5.5V 11.15 Input current DO DO 37 38 39 40 37 38 39 40 DI DI Test Conditions Pin Symbol Min. Typ. Max. Unit Type* Digital Interface (SPI, Control Logic) VVIF 5.5V VVIF = 5.0V 6 6 39 39 39 TSPI tLo,min thi,min tMISOon,max tMISOoff,max tSPIoff,min tCSset,min tCShold,min tsetup,min thold,min Vdig,H Vdig,L Iin,L -0.2 -0.2 -0.2 -60 0 12 0 0 0.48 0.32 100 500 4x 1/fOSCI 2x 1/fOSCI 2x 1/fOSCI 100 100 4.75 0.25 0 0 0 -20 0.2 40 0.2 0.2 0.64 0.48 4 x 1/fOSCI 2x 1/fOSCI 2x 1/fOSCI 100 100 IsupVIF 0.6 1.9 2 3 30 mA A s s s ns ns s s s ns ns V V A A D D D D D D D D D D A A
Vin = 5.5V VVIF = 5.5V
Iin,H
A
A
11.16 11.17 11.18 11.19
Input high level threshold External reset input timing Tristate output leakage current
VVIF = 3.1V
VLH VHL tNRES,min
VVIF VVIF ns nA
A A D A
Input low level threshold VVIF = 3.1V
VMISO = 2.5V
IL,max
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. In this column, pin group names are given. Please refer to Section 2. "Pin Configuration" on page 2 in this document for more details. 2. Operation of coils with higher impedance than the given value is possible but functional limitations might occur (inability to reach to configured coil current). Coils with lower impedance should not be used as they might be detected as faulty.
35
9125F-RKE-09/09
8. Ordering Information
Extended Type Number ATA5279N-PLQW Package VQFN48, 7 mm x 7 mm Remarks Taped and reeled, MOQ 4000
9. Package Information
Package: VQFN_7 x 7_48L Exposed pad 4.5 x 4.5 Dimensions in mm Not indicated tolerances 0.05 Top 48 1 Pin 1 identification 36 37 48 1 Bottom 4.50.15
12
25 24 7 0.2 0.90.1 Z 5.5 13
12
0.5 nom.
Z 10:1
0.40.1
Drawing-No.: 6.543-5137.01-4 Issue: 1; 19.10.06 0.230.07
technical drawings according to DIN specifications
36
ATA5279N [Preliminary]
9125F-RKE-09/09
ATA5279N [Preliminary]
10. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History * * * * * * * * * Features changed Table 2-1 (page 2) changed Page 23: last paragraph changed Text under heading 3.4 "Boost Converter" changed Text under heading 3.6 "Diagnosis" changed New section "4.1 Application Hints" added Table Abs. Max. Ratings changed Table Th. Resistance added Table El. Charactristics changed
9125F-RKE-09/09
9125E-RKE-04/09 9125D-RKE-02/09 9125C-RKE-01/09
* Table "Functional Parameters" item 1.10 added and item 1.3 changed * Section 3.9.2 "General Command Description" on pages 20 to 21 changed * Section 3.9.3 "Driver-related Command Description" on pages 21 to 22 changed * ATA5279 renamed in ATA5279N * Table 3-1 "Sequence for Example 1, Using the Diagnosis Mode" on page 11 changed * Table 3-2 "Sequence for Example 2, Using the Diagnosis Mode" on page 13 changed * Section 4 "Application" on page 26 changed * Section 6 "Functional Parameters" on pages 28 to 32 changed
9125B-RKE-12/08
37
9125F-RKE-09/09
Headquarters
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
International
Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Product Contact
Web Site www.atmel.com Technical Support auto_control@atmel.com Sales Contact www.atmel.com/contacts
Literature Requests www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
(c) 2009 Atmel Corporation. All rights reserved. Atmel (R), Atmel logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
9125F-RKE-09/09

▲Up To Search▲

Price & Availability of ATA5279N

	To Download ATA5279N Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .